The emphasis of this course is an understanding of the system architecture around the processor. Course covers all types of modern semiconductor memory, cache and virtual memory organization, hard disk drives and video-output subsystem. Course gives classification of buses and description of concepts of bus organization, bus protocols, arbitration mechanisms and the concept of Direct Memory Access (DMA). The laboratory projects include design of Cache Controller and VGA-signal generator using VHDL in Xilinx CAD environment. Lect: 3 hrs./Lab: 2 hrs. Prerequisites: (COE 538 or ELE 538) and COE 608 Course Weight: 1.00 Billing Units: 1
